********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Apr 21, 2014
*ECN S14-0883, Rev. A
*File Name: SiR880ADP_PS.txt and SiR880ADP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR880ADP D G S 
M1 3 GX S S NMOS W= 4167000u L= 0.25u 
M2 S GX S D PMOS W= 4167000u L= 0.47u 
R1 D 3 4.30e-03 TC=5.741e-03, 1.769e-05 
CGS GX S 1.579e-09 
CGD GX D 1.000e-13 
RG G GY 1
RTCV 100 S 1e6 TC=1.357e-04, -6.190e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 4167000u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 8.628e-06 NSUB = 1.41e+17 
+ KAPPA = 9.387e-03 NFS = 5.627e+11
+ LD = 0 IS = 0 TPG = 1 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.676e+16 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 6.081e-08 T_MEASURED = 25 BV = 81 
+RS = 5.922e-03 N = 1.022e+00 IS = 7.611e-13 
+EG = 1.124e+00 XTI = 1.109e+00 TRS1 = 1.711e-03 
+CJO = 5.892e-10 VJ = 1.341e+01 M = 5.811e-01 ) 
.ENDS 
